Variable resistance memory devices include a plurality of bit lines and word lines configured to vertically cross the bit lines in cell areas in which data read and write operations are performed. A large parasitic capacitance may be generated between the bit lines and between the word lines due, in part, to dielectric layers configured to fill spaces between the bit lines and between the word lines. The parasitic capacitance between signal wirings of the memory device reduces a read/write operation speed of the memory device. Various techniques for reducing the parasitic capacitance have been discussed.